1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to semiconductor devices that include a fuse part including an antifuse circuit and a protection circuit.
2. Description of the Related Art
In semiconductor devices, such as memory devices, when even a single unit cell includes a defect that causes the cell to function improperly, the device may be regarded as defective. However, it may be counterproductive to discard the whole device due to only a few defective cells. Accordingly, defective cells in a memory device may now be replaced with pre-fabricated redundancy cells to save the device. As a result, yield may increase and production cost may decrease.
A repair procedure using redundancy cells may be performed by fabricating redundancy rows and redundancy columns for a cell array beforehand, and replacing a defective row or column of a memory cell with a redundancy row or column. For example, when a defective memory cell is detected through testing after wafer processing is completed, a program may be executed in an internal circuit to replace an address of the defective cell with an address of a redundancy cell. Accordingly, when an address signal corresponding to a defective line is input during operation of the semiconductor memory device, the device accesses a spare line instead of the defective line.
A typical repair procedure involves the use of a fuse, in which a fuse is disposed in an internal circuit for performing a repair, and a row or column having a defective cell is replaced with a redundancy row or column by a technique of melting a fuse on a line connected to the defective row or column by overcurrent, a technique of cutting the fuse with a laser beam, a technique of connecting a junction with a laser beam, or a technique of programming the cell as an EPROM, etc. Among these techniques, the technique of cutting a fuse with a laser beam has been widely used because of its simplicity, reliability, and low probability of programming error. In this technique, a fuse having a polysilicon or metal interconnection may be used. However, the method of repairing a semiconductor device using a fuse is typically carried out in a wafer state and may not be applied when a cell proves to be defective after packaging is completed. To overcome this limitation, a method of using an antifuse has been developed.
Antifuses can be simply programmed for repairing defects in the packaging procedure. In general, an antifuse device has an opposite electrical characteristic to a fuse device. That is, the antifuse is generally a resistant fuse device that has high resistance (e.g., 100 MΩ) in an unprogrammed state and low resistance (i.e., 100 kΩ or less) after a programming operation. An antifuse device is generally made of thin dielectric materials, such as a complex in which a dielectric, for example, silicon dioxide (SiO2), silicon nitride, tantalum oxide, or silicon dioxide-silicon nitride-silicon dioxide (ONO), is inserted between two conductors. The antifuse is programmed by destroying the dielectric between the conductors by applying a high voltage (e.g., 10V) across terminals of the antifuse for a long-enough time. Therefore, when the antifuse is programmed, the conductors at both ends thereof are shorted, and its resistance is reduced.
A typical repair circuit that includes an antifuse has a structure such as that illustrated in FIG. 1, comprising: an antifuse circuit part 10 that includes a plurality of antifuse circuits that receive a program mode selection signal SEL for identifying a programming mode in which the antifuse is fused, and an address signal ADDR for selecting a certain antifuse to be fused; a power-up signal generator 20 that outputs to the antifuse circuit part 10 a power-up signal PRECH for detecting power stabilization after application of power to a chip; a high voltage generator 30 that fuses the selected antifuse by applying a high voltage to the antifuse circuit part 10; and a redundancy circuit 40 that activates a redundancy cell in response to a redundancy signal RD output from the antifuse circuit part 10.
FIG. 2 illustrates the antifuse circuit part 10 of the repair circuit illustrated in FIG. 1 according to a conventional implementation. Although FIG. 2 illustrates two antifuse circuits 11 and 12 connected to a pad PAD that receive a high voltage generated by a high voltage generator 30 of FIG. 1, in general, a plurality of antifuse circuits 11 and 12 corresponding to one row or column are connected to the pad PAD.
However, in the antifuse circuits 11 and 12 having such a configuration, when the high voltage is applied to the pad PAD to fuse one of the antifuse circuits, a gate dielectric layer of a transistor forming another of the antifuse circuits 11 and 12 connected together to the pad PAD may be damaged. This will now be described in more detail with reference to FIG. 2.
For example, suppose that only a first antifuse FUSE1 of a first antifuse circuit 11 is to be fused. The antifuse circuits 11 and 12 may have NMOS transistors N11 and N21 as a switch part, one end of which is a fuse part and the other end of which is a latch part.
The NMOS transistors N11 and N21 of the switch part switch between fuse nodes Node11 and Node21 and latch nodes Node12 and Node22 in response to a power-up signal PRECH. The power-up signal PRECH is produced using a power voltage Vcc. At the beginning of power application, the power-up signal PRECH increases as the power voltage Vcc increases, and when the power voltage Vcc reaches a certain level, the power-up signal PRECH is maintained at the same level as the power voltage Vcc for a predetermined time. Accordingly, when the power voltage Vcc is applied, the power-up signal PRECH increases and then is maintained at a fixed level for a predetermined time, and, thus, current may flow from the latch nodes Node12 and Node22 to the fuse nodes Node11 and Node21.
A program mode selection signal SEL and address signals ADDR1 and ADDR2 are applied to the fuse part. A semiconductor memory device activates the program mode selection signal SEL to perform a repair procedure after a defective memory cell is detected through testing. The program mode selection signal SEL may be applied to the plurality of antifuse circuits 11 and 12 at the same time so as to perform programming operations. Meanwhile, the semiconductor memory device activates the address signal ADDR1 of the antifuse circuit 11 corresponding to the defective memory cell detected by the testing. That is, the program mode selection signal SEL is activated during the programming operation and applied to all antifuse circuits 11 and 12, and the address signals ADDR1 and ADDR2 are selectively activated to choose only the antifuse circuit to be programmed among the plurality of antifuse circuits 11 and 12.
In the programming operation, the program mode selection signal SEL is activated, as is the first address signal ADDR1, because the first antifuse FUSE1 is to be fused; however the second address signal ADDR2 is not activated because no fusing is to be performed there. In this case, an activated signal may have a logic high level.
The high level program mode selection signal SEL and first address signal ADDR1 are input to a NAND gate NAND1 which, in response, outputs a low level signal. This low level signal is then input to a first inverter INV1 that outputs a high level signal, which is applied to a gate terminal of an NMOS transistor N12. The NMOS transistor N12 is turned on in response to the high level signal. Because the second address signal ADDR2 is applied at a low level, a low level signal is applied to a gate terminal of an NMOS transistor N22, which is consequently turned off.
In the meantime, when a high voltage Vf is applied from the high voltage generator 30 of FIG. 1 to the pad PAD, the high voltage is applied to one end of all antifuses FUSE1 and FUSE2 connected with the pad PAD. In addition, the NMOS transistor N12 is turned on by the program mode selection signal SEL and the first address signal ADDR1, and an NMOS transistor N13 is always turned on because a boost voltage Vpp is applied to a gate terminal. Thus, an A node NodeA is brought to a ground voltage Vss and a high voltage is applied between both ends of the first antifuse FUSE1 fusing the first antifuse FUSE1. An NMOS transistor N22 of a second antifuse circuit 12 is turned off responsive to the low level second address signal ADDR2 so that a voltage applied between both ends of the second antifuse FUSE2 is not high and, thus, the second antifuse FUSE2 is not fused. The high voltage Vf is applied to the pad PAD during a fusing operation, and the ground voltage Vss is applied to the pad PAD when the fusing operation is not performed.
NMOS transistors N13 and N23 interconnected between the fuse node Node11 and the A node NodeA, and between the fuse node Node21 and a B node NodeB may function to prevent or reduce damage to gate oxide layers of the transistors included in each of the antifuse circuits 11 and 12, even if the high voltage is applied to the pad PAD in programming.
As described above, in the antifuse circuits 11 and 12 in which the first antifuse FUSE1 is fused and the second antifuse FUSE2 is not fused, the latch part precharges the latch nodes Node21 and Node22 with the power voltage Vcc and, in turn, latches the voltage thereof.
As the power voltage Vcc increases at the beginning of power application, the latch part precharges the latch nodes Node21 and Node22. A power stabilization signal VCCH is maintained at a “low” level during the increase in the power voltage Vcc, and when the power voltage Vcc reaches a certain level and is maintained, the power stabilization signal VCCH transitions to a “high” level. Upon initial application of power, the power stabilization signal VCCH is at a low level so that a current path is formed by PMOS transistors P11, P21, P12 and P22. Also, the power-up signal PRECH increases as the power voltage Vcc increases, and, thus, current flows toward the fuse nodes Node11 and Node21 through the PMOS transistors P11, P21 P12 and P22 and the NMOS transistors N11 and N21. Gate terminals of the NMOS transistors N13 and N23 are connected to a boost voltage Vpp, and, thus, current flows to the antifuses FUSE1 and FUSE2.
The first antifuse FUSE1 of the first antifuse circuit 11 is fused so as to have small resistance, and, thus, current through the fuse node Node11 flows to the pad PAD through the first antifuse FUSE1 so that a voltage of the fuse node Node11 does not increase beyond a predetermined level. The NMOS transistor N11 connects the fuse node Node11 and the latch node Node12 in response to the power-up signal PRECH, and, thus, the voltage of the latch node Node12 decreases according to the voltage of the fuse node Node11. When the power voltage Vcc is stable, the power stabilization signal VCCH transitions to a high level, the PMOS transistor P12 is turned off, and an NMOS transistor N14 is turned on. As the voltage of the latch node Node12 decreases, a second inverter INV12 outputs a high level signal, and, thus, an NMOS transistor N15 is turned on and the PMOS transistor P13 is turned off. Thus, the voltage of the latch node Node12 is stabilized at a low level. Because the NMOS transistor N14 is turned on, it can be seen that the second inverter INV12, the PMOS transistor P13, and the NMOS transistor N15 constitute a latch circuit.
The second antifuse FUSE2 of the second antifuse circuit 12 is not fused and, thus, has a large resistance so that the current through the fuse node Node 21 does not flow to the pad PAD through the second antifuse FUSE2. Accordingly, the voltage at the fuse node Node21 increases. The NMOS transistor N21 connects the fuse node Node21 and the latch node Node22 in response to the power-up signal PRECH, and, thus, the voltage of the latch node Node22 increases according to the voltage of the fuse node Node21. When the power voltage Vcc is stable, the power stabilization signal VCCH transitions to a high level, the PMOS transistor P22 is turned off, and an NMOS transistor N24 is turned on. As the voltage of the latch node Node22 increases, a second inverter INV22 outputs a low level signal, and, thus, an NMOS transistor N25 is turned off and the PMOS transistor P23 is turned on. As a result, the voltage at the latch node Node22 is stabilized at a high level. Because the NMOS transistor N24 is turned on, it can be seen that the second inverter INV22, the PMOS transistor P23, and the NMOS transistor N25 constitute a latch circuit.
When the antifuse FUSE1 of the antifuse circuit 11 is fused and the antifuse FUSE2 of the second antifuse circuit 12 is not fused by the programming operation, the first antifuse circuit 11 outputs a high level redundancy signal RD1 and the second antifuse circuit 12 outputs a low level redundancy signal RD2.
When the high voltage Vf is applied from the high voltage generator 30 through the pad PAD to the first antifuse FUSE1 of the first antifuse circuit 11 in the programming operation, the high voltage Vf is applied to one end of the second antifuse FUSE2 of the second antifuse circuit 12 as well as the first antifuse circuit 11, but the NMOS transistor N22 in the second antifuse circuit 12 is not turned on. As a result, the B node NodeB is in a floating state and its voltage level increases from an initial value Vcc-Vth due to a coupling effect. The increase in voltage level is given by the following Formula 1 in terms of the capacitance Cnode of the NodeB, the capacitance Cfuse of the second antifuse FUSE2 and the pad PAD:
                                          C            fuse                                              C              fuse                        +                          C              node                                      ×                  V          f                                    [                  FORMULA          ⁢                                          ⁢          1                ]            
In the conventional art, when the voltage of the B node NodeB increases, a relatively high load is applied to a gate oxide layer of the NMOS transistor N23 adjacent to the B node NodeB due to the coupling effect. As a result, the gate oxide layer of the NMOS transistor N23 may sustain damage, such as cracks, or be destroyed.